No on-chip peripherals (SCI/SPI/timer/ADC) #7

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opened 2026-08-24 11:44:21 +02:00 by sid · 0 comments

sid commented

2026-08-24 11:44:21 +02:00

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Summary

The shipped platform (platforms/cpus/m68hc12.repl) contains only the CPU, a
16 KiB RAM, a 16 KiB ROM and a 64-byte vector table:

sysbus:
    Endianess: Endianess.BigEndian

cpu: CPU.M68HC12 @ sysbus
    cpuType: "m68hc12"

ram: Memory.ArrayMemory @ sysbus 0x0000
    size: 0x4000

rom: Memory.ArrayMemory @ sysbus 0xC000
    size: 0x3FC0

vectorTable: Memory.MappedMemory @ sysbus 0xFFC0
    size: 0x40

No on-chip peripheral (SCI serial, SPI, ECT/TPM timers, ATD/ADC, PWM, CAN,
etc.) is modeled. This is expected for a CPU-core port, but it means real
firmware that initializes and uses the chip's register block cannot run.

Impact

Bare-metal code that reads/writes the on-chip register map (typically
0x0000-0x03FF) touches unmapped memory instead of a peripheral.
No way to do serial console I/O (SCI), timing loops (timer channels), ADC
reads, etc., so firmware with any peripheral use fails at boot.
There is no specific HC12 chip selected (the 68HC12 line spans many
devices with different register maps and pinouts).

Current behavior

Only memory regions exist; ReadByte/WriteByte to any other address hits
whatever the bus maps there (or reports a bus error).

Affected files

platforms/cpus/m68hc12.repl (platform description)
New peripherals under
src/Infrastructure/src/Emulator/Peripherals/Peripherals/ (e.g. a
M68HC12_SCI, M68HC12_ECT), following existing Renode peripheral
conventions.

Desired behavior

At minimum, a specific, real HC12/HCS12 part is chosen and its on-chip
register block is mapped:

Memory map: the device's register block placed at its real base
address in a new .repl platform (keep the bare CPU platform as the
minimal reference).
Minimum working set: the registers firmware needs to boot and talk to
the outside world — typically the SCI (serial console, backed by a
UARTBackend so Renode's uart/emulation CreateUartPty plumbing works),
and enough of the timer/ECT module to make delay loops and interrupt
timing functional.
Interrupt wiring: peripheral interrupts drive the CPU's IRQ/XIRQ GPIO
lines (OnGPIO, M68HC12.cs:85-95) so the vector table is actually used.

Acceptance criteria

A chosen device platform (platforms/cpus/<device>.repl) loads and maps the
register block at the correct addresses.
Writing firmware that uses the SCI for printf-style output works through a
Renode UART backend (visible in the monitor / a PTY).
Timer-driven interrupts fire and vector correctly through the existing IRQ
path.
The existing bare m68hc12.repl platform keeps working unchanged.

Suggested approach / scope note

This is a large, device-specific effort; do it in stages: pick one
well-documented part (e.g. an S12 or S12X with public register manual), model
only the modules firmware actually needs first, then grow.
Reuse Renode's existing UART/timer patterns rather than writing new
infrastructure.
Document clearly which device and which modules are covered vs. not.

## Summary The shipped platform (`platforms/cpus/m68hc12.repl`) contains only the CPU, a 16 KiB RAM, a 16 KiB ROM and a 64-byte vector table: ```yaml sysbus: Endianess: Endianess.BigEndian cpu: CPU.M68HC12 @ sysbus cpuType: "m68hc12" ram: Memory.ArrayMemory @ sysbus 0x0000 size: 0x4000 rom: Memory.ArrayMemory @ sysbus 0xC000 size: 0x3FC0 vectorTable: Memory.MappedMemory @ sysbus 0xFFC0 size: 0x40 ``` No on-chip peripheral (SCI serial, SPI, ECT/TPM timers, ATD/ADC, PWM, CAN, etc.) is modeled. This is expected for a CPU-core port, but it means real firmware that initializes and uses the chip's register block cannot run. ## Impact - Bare-metal code that reads/writes the on-chip register map (typically `0x0000-0x03FF`) touches unmapped memory instead of a peripheral. - No way to do serial console I/O (SCI), timing loops (timer channels), ADC reads, etc., so firmware with any peripheral use fails at boot. - There is no specific HC12 chip selected (the 68HC12 line spans many devices with different register maps and pinouts). ## Current behavior - Only memory regions exist; `ReadByte`/`WriteByte` to any other address hits whatever the bus maps there (or reports a bus error). ## Affected files - `platforms/cpus/m68hc12.repl` (platform description) - New peripherals under `src/Infrastructure/src/Emulator/Peripherals/Peripherals/` (e.g. a `M68HC12_SCI`, `M68HC12_ECT`), following existing Renode peripheral conventions. ## Desired behavior At minimum, a **specific, real HC12/HCS12 part** is chosen and its on-chip register block is mapped: 1. **Memory map:** the device's register block placed at its real base address in a new `.repl` platform (keep the bare CPU platform as the minimal reference). 2. **Minimum working set:** the registers firmware needs to boot and talk to the outside world — typically the **SCI** (serial console, backed by a `UARTBackend` so Renode's `uart`/`emulation CreateUartPty` plumbing works), and enough of the **timer/ECT** module to make delay loops and interrupt timing functional. 3. **Interrupt wiring:** peripheral interrupts drive the CPU's IRQ/XIRQ GPIO lines (`OnGPIO`, `M68HC12.cs:85-95`) so the vector table is actually used. ## Acceptance criteria - A chosen device platform (`platforms/cpus/<device>.repl`) loads and maps the register block at the correct addresses. - Writing firmware that uses the SCI for `printf`-style output works through a Renode UART backend (visible in the monitor / a PTY). - Timer-driven interrupts fire and vector correctly through the existing IRQ path. - The existing bare `m68hc12.repl` platform keeps working unchanged. ## Suggested approach / scope note - This is a large, device-specific effort; do it in stages: pick one well-documented part (e.g. an S12 or S12X with public register manual), model only the modules firmware actually needs first, then grow. - Reuse Renode's existing UART/timer patterns rather than writing new infrastructure. - Document clearly which device and which modules are covered vs. not.

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sid/renode-m68hc12#7

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