sid/renode-m68hc12
1
0
Fork 0
Code Issues 6 Pull requests 1 Projects Releases Packages Wiki Activity Actions

Special/fuzzy-logic instructions trap instead of executing #2

New issue
Open
opened 2026-08-24 11:42:24 +02:00 by sid · 0 comments
sid commented 2026-08-24 11:42:24 +02:00
Owner
Copy link

Summary

The following CPU12 instructions are decoded but, on execution, hit the
Trap() fallback (M68HC12.cs:585-590): a warning is logged and the CPU
vectors to the unimplemented-opcode trap vector $FFF8 instead of executing
the instruction:

  • MAXA / MINA — 8-bit unsigned max/min into accumulator A
  • EMAXD / EMIND — 16-bit unsigned max/min into accumulator D
  • MAXM / MINM — 8-bit unsigned max/min into memory
  • EMAXM / EMINM — 16-bit unsigned max/min into memory
  • TBL / ETBL — table lookup and interpolate
  • EMACS — extended multiply and accumulate (signed 16x16 to 32-bit)
  • WAV — weighted average (fuzzy logic)
  • REV / REVW — fuzzy-logic rule evaluation
  • MEM — membership function (fuzzy logic)

Current behavior

case "MAXA": case "MINA": case "EMAXD": case "EMIND":
case "MAXM": case "MINM": case "EMAXM": case "EMINM":
case "TBL": case "ETBL": case "EMACS": case "WAV":
case "REV": case "REVW": case "MEM":
    Trap();
    break;

Trap() (M68HC12.cs:601) logs Unimplemented opcode trap at 0x... and
services the $FFF8 vector, pushing a 9-byte interrupt frame. Execution of
programs that use any of these instructions is therefore broken, not just
unaccelerated.

Impact

Firmware using the CPU12's fuzzy-logic instruction set (a headline feature of
the architecture) or the max/min / table-lookup helpers crashes into the trap
handler. This is the single largest functional gap in the port.

Affected files

  • src/Infrastructure/src/Emulator/Peripherals/Peripherals/CPU/M68HC12/M68HC12.cs (ExecuteOneInstruction switch, M68HC12.cs:585-590)
  • Tests: add to existing suites or new files under
    src/Infrastructure/src/Emulator/Main/Tests/UnitTests/

Desired behavior

Each instruction executes with the register/memory and CCR effects given in
the CPU12RG summary (docs/m68hc12/02-instruction-set.md,
docs/m68hc12/reference/CPU12RG-instruction-set-summary.txt, and the
hcs12_instruction_set.md table at the repo root). REV/REVW/MEM/WAV
are the fuzzy-logic primitives and carry "?" (undefined) CCR semantics that
must be matched per the manual.

Acceptance criteria

  • No instruction in the list above traps; each produces the documented result.
  • CCR flags (N/Z/V/C, and H where applicable) match the CPU12RG rows for a
    representative set of inputs.
  • Unit tests added for each mnemonic's primary form and its CCR behavior,
    registered in UnitTests.csproj (non-globbing).
  • Full M68HC12 suite passes: 
    dotnet test src/Infrastructure/src/Emulator/Main/Tests/UnitTests/UnitTests_NET.csproj -c Release --filter "M68HC12"

Suggested approach

  • The GDB simulator sources in docs/m68hc12/reference/gdb-sim-m68hc11-interp.c
    implement every one of these and are the best behavioral cross-check — but
    they are GPL; consult as reference only, do not copy (Renode is BSD).
  • MAXA/MINA/EMAXD/EMIND are straightforward compares; MAXM/MINM/EMAXM/EMINM
    read-modify-write memory. TBL/ETBL interpolate between two table entries
    using the fraction register. EMACS reads/writes a 32-bit accumulator in
    memory. MEM/REV/REVW/WAV operate over the fuzzy-logic rule table in memory
    with X/Y/D pointers.
  • Handle in the same style as existing switch cases; fetch operands via the
    existing ComputeEffectiveAddress / ReadOperandByte / ReadOperandWord
    helpers.
## Summary The following CPU12 instructions are decoded but, on execution, hit the `Trap()` fallback (`M68HC12.cs:585-590`): a warning is logged and the CPU vectors to the unimplemented-opcode trap vector `$FFF8` instead of executing the instruction: - `MAXA` / `MINA` — 8-bit unsigned max/min into accumulator A - `EMAXD` / `EMIND` — 16-bit unsigned max/min into accumulator D - `MAXM` / `MINM` — 8-bit unsigned max/min into memory - `EMAXM` / `EMINM` — 16-bit unsigned max/min into memory - `TBL` / `ETBL` — table lookup and interpolate - `EMACS` — extended multiply and accumulate (signed 16x16 to 32-bit) - `WAV` — weighted average (fuzzy logic) - `REV` / `REVW` — fuzzy-logic rule evaluation - `MEM` — membership function (fuzzy logic) ## Current behavior ```csharp case "MAXA": case "MINA": case "EMAXD": case "EMIND": case "MAXM": case "MINM": case "EMAXM": case "EMINM": case "TBL": case "ETBL": case "EMACS": case "WAV": case "REV": case "REVW": case "MEM": Trap(); break; ``` `Trap()` (`M68HC12.cs:601`) logs `Unimplemented opcode trap at 0x...` and services the `$FFF8` vector, pushing a 9-byte interrupt frame. Execution of programs that use any of these instructions is therefore broken, not just unaccelerated. ## Impact Firmware using the CPU12's fuzzy-logic instruction set (a headline feature of the architecture) or the max/min / table-lookup helpers crashes into the trap handler. This is the single largest functional gap in the port. ## Affected files - `src/Infrastructure/src/Emulator/Peripherals/Peripherals/CPU/M68HC12/M68HC12.cs` (`ExecuteOneInstruction` switch, `M68HC12.cs:585-590`) - Tests: add to existing suites or new files under `src/Infrastructure/src/Emulator/Main/Tests/UnitTests/` ## Desired behavior Each instruction executes with the register/memory and CCR effects given in the CPU12RG summary (`docs/m68hc12/02-instruction-set.md`, `docs/m68hc12/reference/CPU12RG-instruction-set-summary.txt`, and the `hcs12_instruction_set.md` table at the repo root). `REV`/`REVW`/`MEM`/`WAV` are the fuzzy-logic primitives and carry "?" (undefined) CCR semantics that must be matched per the manual. ## Acceptance criteria - No instruction in the list above traps; each produces the documented result. - CCR flags (N/Z/V/C, and H where applicable) match the CPU12RG rows for a representative set of inputs. - Unit tests added for each mnemonic's primary form and its CCR behavior, registered in `UnitTests.csproj` (non-globbing). - Full M68HC12 suite passes: ```bash dotnet test src/Infrastructure/src/Emulator/Main/Tests/UnitTests/UnitTests_NET.csproj -c Release --filter "M68HC12" ``` ## Suggested approach - The GDB simulator sources in `docs/m68hc12/reference/gdb-sim-m68hc11-interp.c` implement every one of these and are the best behavioral cross-check — but they are GPL; consult as reference only, do not copy (Renode is BSD). - `MAXA/MINA/EMAXD/EMIND` are straightforward compares; `MAXM/MINM/EMAXM/EMINM` read-modify-write memory. `TBL/ETBL` interpolate between two table entries using the fraction register. `EMACS` reads/writes a 32-bit accumulator in memory. `MEM/REV/REVW/WAV` operate over the fuzzy-logic rule table in memory with `X`/`Y`/`D` pointers. - Handle in the same style as existing switch cases; fetch operands via the existing `ComputeEffectiveAddress` / `ReadOperandByte` / `ReadOperandWord` helpers.
Sign in to join this conversation.
No Branch/Tag specified
Branches Tags
master
upstream
No results found.
Labels
Clear labels
No items
No labels
Milestone
Clear milestone
No items
No milestone
Projects
Clear projects
No items
No project
Assignees
Clear assignees
No assignees
1 participant
Notifications
Due date
The due date is invalid or out of range. Please use the format "yyyy-mm-dd".

No due date set.

Dependencies

No dependencies set.

Reference
sid/renode-m68hc12#2
No description provided.