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Expand full-chip simulation: more S12/S12X peripheral models #7

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opened 2026-09-24 09:55:03 +02:00 by sid · 0 comments
sid commented 2026-09-24 09:55:03 +02:00
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CodeWarrior's full-chip simulator models the complete on-chip peripheral set for each supported device (ADC, PWM, ECT/TIM, SPI, SCI, CAN, I2C, RTC, flash controller, etc.) with per-device register maps and timing. This repo's gdb-sim models only a handful of peripherals, so most S12/S12X firmware cannot be exercised on the host.

Current state

  • The m68hc11 simulator (GDB 17.2) provides the classic HC11 devices (m68hc11sio, m68hc11tim, m68hc11spi, m68hc11eepr, nvram).
  • S12 additions (via patches/sim-s12-peripherals.patch + patches/sim-model/*): s12sci1 (SCI1 @ 0xD0), s12tim0 (TIM0 @ 0x80), s12gpio (Port B @ 0x01). The MC68HC12 EEPROM was moved to 0x4000-0x47FF (patches/sim-m68hc12-eeprom.patch).
  • No ADC, PWM, ECT beyond TIM0, SPI master on S12, CAN, I2C, flash controller, or XGATE core. tests/s12/run-vectors.sh notes one vector is "mock-only" because uart.write has no hardware counterpart.

Motivation

  • Firmware that touches peripherals beyond SCI1/TIM0/GPIO cannot be simulated, breaking the "build + run in CI" workflow this repo is built around.
  • Peripheral-accurate simulation is what makes the existing S12 timer/vector byte-diff tests meaningful.

Proposed scope

  • Model additional common S12/S12X peripherals in sim/m68hc11, matching the existing s12_*.c/dv-*.c device pattern:
    • SCI0 and full SCI1 feature set (interrupts, error flags),
    • SPI master/slave with external device interaction,
    • ECT (enhanced capture timer) channels beyond ch0,
    • 8/10-bit ADC with conversion timing,
    • PWM channels,
    • a flash/EEPROM controller for code-in-RAM and self-programming tests,
    • (stretch) CAN and I2C.
  • Per-device register map tables (from the device support pack, issue #03).
  • XGATE core co-simulation so issue #04's C-to-XGATE flows can be tested.

Acceptance criteria

  • Firmware for each newly modeled peripheral compiles for -m68hc12/-m9s12x and passes a byte-diff/register-trace test under target sim (same pattern as tests/s12/run-vectors.sh).
  • Removing the "mock-only" status of vec3 in tests/s12/run-vectors.sh.
  • No regressions in the existing check-sim-* and s12-* checks in flake.nix.

References

  • patches/sim-s12-peripherals.patch, patches/sim-model/*
  • patches/sim-m68hc12-eeprom.patch
  • tests/sim-model/*, tests/s12/* (harness)
  • pkgs/gdb-sim.nix (device wiring)
CodeWarrior's full-chip simulator models the complete on-chip peripheral set for each supported device (ADC, PWM, ECT/TIM, SPI, SCI, CAN, I2C, RTC, flash controller, etc.) with per-device register maps and timing. This repo's `gdb-sim` models only a handful of peripherals, so most S12/S12X firmware cannot be exercised on the host. ## Current state - The m68hc11 simulator (GDB 17.2) provides the classic HC11 devices (`m68hc11sio`, `m68hc11tim`, `m68hc11spi`, `m68hc11eepr`, `nvram`). - S12 additions (via `patches/sim-s12-peripherals.patch` + `patches/sim-model/*`): `s12sci1` (SCI1 @ 0xD0), `s12tim0` (TIM0 @ 0x80), `s12gpio` (Port B @ 0x01). The MC68HC12 EEPROM was moved to 0x4000-0x47FF (`patches/sim-m68hc12-eeprom.patch`). - No ADC, PWM, ECT beyond TIM0, SPI master on S12, CAN, I2C, flash controller, or XGATE core. `tests/s12/run-vectors.sh` notes one vector is "mock-only" because `uart.write` has no hardware counterpart. ## Motivation - Firmware that touches peripherals beyond SCI1/TIM0/GPIO cannot be simulated, breaking the "build + run in CI" workflow this repo is built around. - Peripheral-accurate simulation is what makes the existing S12 timer/vector byte-diff tests meaningful. ## Proposed scope - Model additional common S12/S12X peripherals in `sim/m68hc11`, matching the existing `s12_*.c`/`dv-*.c` device pattern: - SCI0 and full SCI1 feature set (interrupts, error flags), - SPI master/slave with external device interaction, - ECT (enhanced capture timer) channels beyond ch0, - 8/10-bit ADC with conversion timing, - PWM channels, - a flash/EEPROM controller for code-in-RAM and self-programming tests, - (stretch) CAN and I2C. - Per-device register map tables (from the device support pack, issue #03). - XGATE core co-simulation so issue #04's C-to-XGATE flows can be tested. ## Acceptance criteria - Firmware for each newly modeled peripheral compiles for `-m68hc12`/`-m9s12x` and passes a byte-diff/register-trace test under `target sim` (same pattern as `tests/s12/run-vectors.sh`). - Removing the "mock-only" status of `vec3` in `tests/s12/run-vectors.sh`. - No regressions in the existing `check-sim-*` and `s12-*` checks in `flake.nix`. ## References - `patches/sim-s12-peripherals.patch`, `patches/sim-model/*` - `patches/sim-m68hc12-eeprom.patch` - `tests/sim-model/*`, `tests/s12/*` (harness) - `pkgs/gdb-sim.nix` (device wiring)
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sid/m68hc11-toolchain#7
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